The invention relates generally to data processing and more particularly to a method and apparatus for combining multiple line data elements to produce resultant line data elements in a video graphics system.
Generating a video graphics display typically involves generating a number of lines of video data that are provided to a display, where each line is generated on the display to produce the desired video image. In many cases, the data provided to the display is the result of processing operations that scale or filter the video information to produce resulting effects or to configure the lines of data to suit the requirements of the display. In filtering and scaling operations, the resultant pixels for a display line are often generated using a number of lines of data. For example, a three-tap filter may use data from three lines of image data to produce each resultant line.
In many applications, the lines of data to be filtered or scaled are stored in memory located external to the integrated circuit performing the data processing that produces the resultant line. In such systems, the data is often fetched from the memory and stored within an on-chip cache memory, or some other memory block located on the chip. Once the data has been brought on-chip, it is retrieved from the on-chip memory and used for the filtering, scaling, or similar operation. In some systems, data elements may be used multiple times in the filtering or scaling process. For example, in a three-tap filtering system, the fourth resultant line may be generated using the third, fourth, and fifth lines of image data, and the fifth resultant line is generated using the fourth, fifth, and sixth lines of image data. In these systems, efficiency is increased if data is reused once it is loaded into the on-chip memory, as fetching the data from off-chip consumes memory and processor bandwidth. Thus, if the fourth and fifth lines could be maintained for use in generating both the fourth and fifth lines of data, system efficiency would be increased. In order to be able to reuse data stored in the cache memory, the data must be allowed to remain present on-chip until the additional processing that utilizes that data occurs.
Unfortunately, some operations involve lines of data that include a large number of data elements. In the case where many lines of data are used to generate a single resultant line, storing all of the lines for processing can be problematic in terms of the amount of memory required.
Therefore, a need exists for method and apparatus for combining line data elements that allows for reuse of data elements loaded into on-chip memory where the amount of memory needed to store the data is less than that needed to store the full set of data required to produce a single resultant line.